1. Field of the Invention
The invention relates generally to the fabrication of semiconductor devices and to polishing and planarizing of substrates.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large-scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
Multilevel interconnects are formed by the sequential deposition and removal of materials from the substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material and in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing media in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing media. The substrate and polishing media are moved in a relative motion to one another.
A polishing composition is provided to the polishing media to effect chemical activity in removing material from the substrate surface. The polishing composition may contain abrasive material to enhance the mechanical activity between the substrate and polishing media. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing media while dispersing a polishing composition to effect both chemical activity and mechanical activity. The chemical and mechanical activity removes excess deposited materials as well as planarizing a substrate surface.
Chemical mechanical polishing may be used in the fabrication of shallow trench isolation (STI) structures. STI structures may be used to separate transistors and components of a transistor, such as source/drain junctions or channel stops, on a substrate surface during fabrication. STI structures can be formed by depositing a series of dielectric materials and polishing the substrate surface to remove excess or undesired dielectric materials. An example of a STI structure includes depositing a silicon nitride layer on an oxide layer formed on a silicon substrate surface, patterning and etching the substrate surface to form a feature definition, depositing a silicon oxide fill of the feature definitions, and polishing the substrate surface to remove excess silicon oxide to form a feature. The silicon nitride layer may perform as a barrier layer, a hard mask during etching of the features in the substrate and/or as a polishing stop during subsequent polishing processes. Such STI fabrication processes require polishing the silicon oxide layer to the silicon nitride layer with a minimal amount of silicon nitride removed during the polishing process in order to prevent damaging of the underlying materials, such as oxide and silicon.
The STI substrate is typically polished using conventional, abrasive-free, polishing media and an abrasive containing polishing slurry. However, polishing STI substrates with conventional polishing articles and abrasive containing polishing slurries has been observed to result in overpolishing of the substrate surface and forming recesses in the STI features and other topographical defects such as microscratches on the substrate surface. This phenomenon of overpolishing and forming recesses in the STI features is referred to as dishing. Dishing is highly undesirable because dishing of substrate features may detrimentally affect device fabrication by causing failure of isolation of transistors and transistor components from one another resulting in short-circuits. Additionally, overpolishing of the substrate may also result in nitride loss and exposing the underlying silicon substrate to damage from polishing or chemical activity, which detrimentally affects device quality and performance.
FIGS. 1A–1C are schematic diagrams illustrating the phenomena of dishing and nitride loss. FIG. 1A shows an example of a patterned STI substrate with a substrate 10, having a thermal oxide layer 15 disposed thereon, a polishing/etch stop layer 20, such as silicon nitride, disposed on the thermal oxide layer 15, and patterned to have feature definitions 35. The feature definitions 35 are then filled with a dielectric fill material 30, such as a silicon oxide material, with excess dielectric fill material 40 formed over the feature definitions 35 and silicon nitride layer 20.
FIG. 1B illustrates the phenomena of dishing observed with polishing by conventional techniques to remove the excess dielectric fill material 40. During polishing of the silicon oxide material 30 to the silicon nitride layer 20, the silicon oxide material 30 may be overpolished to remove any residual dielectric fill material 30, which may result in surface defects, such as recesses 45, formed in the dielectric fill material 30 in the feature definitions 35. The amount of dishing 50 from the desired amount of dielectric fill material 30 in the feature definitions 35 is represented by dashed lines.
FIG. 1C illustrates nitride loss from the surface of the silicon nitride layer 20 from excess polishing of the substrate surface with conventional polishing processes. Silicon nitride loss may take the form of excess removal of silicon nitride, or “thinning” of the silicon nitride layer, from the desired amount 60 of silicon nitride. Silicon nitride loss may also be premature removal of the silicon nitride layer and exposing the underlying oxide layer 15 and substrate material 10. The silicon nitride loss may render the silicon nitride layer 30 unable to prevent or limit damage to or contamination of the underlying substrate material during polishing or subsequent processing.
STI polishing with fixed-abrasive polishing articles have shown reduced dishing and improved polishing uniformity compared with conventional slurry polishing processes. A fixed-abrasive polishing article generally contains fixed-abrasive particles held in a containment media, or binder, which provides mechanical activity to the substrate surface, along with a plurality of geometric abrasive composite elements adhered to the containment media. However, conventional fixed-abrasive polishing processes have an inherently low removal rate of oxide material thereby increasing polishing times and reducing substrate throughput. Increased processing time may also occur in conventional deposition processes that use excess material deposition on the substrate surface, referred to as overfill, to ensure fill of features formed in the substrate surface.
Several approaches have been examined for limiting the extent of oxide overfill in forming STI features for improved processing throughput. One approach includes using multiple deposition, for example high density plasma chemical vapor deposition (HDP CVD) and etching steps to deposit, etch back, and re-fill substrate features. Another approach uses a sputter or etching process to thin the overfill deposited on the substrate surface. Other approaches include using a post deposition wet etch process to etch the oxide film so that there is still topography remaining for use with fixed-abrasive polishing articles. However, these processes have been observed to increase integration complexity and also have increased processing times and reduced substrate throughput.
Therefore, there exists a need for a method and polishing composition that facilitates the removal of dielectric materials with minimal or reduced defect formation during polishing of a substrate surface.